The MIP (Memory In Pixel) technology has been proposed for including a memory in each pixel, for providing the data written into the pixel while the active-matrix type display device is in the static image display mode. Thus, the data write-in process of the driver can thus be substituted, and the power-consumption can also be decreased, as described in U.S. Pat. No. 6,897,843 and US Pub. 2002/084463, which is incorporated herein by reference.
Generally, in the MIP technology, for maintaining the data stored in the memory of each pixel, a DRAM (Dynamic Random Access Memory) or a SRAM (Static Random Access Memory) could be used. The SRAM consists of a circuit, which has plural transistors arranged in sequence. The DRAM consists of a transistor and a capacitor. Thus, the DRAM is preferred in the respect of minimizing the covering area of the circuit and reducing the spacing between the pixels. However, for maintaining the small charge stored in the capacitor of the DRAM, a refreshing process has to be executed regularly. An example of the pixel circuit using the DRAM therein can be found in US Pub. 2007/040785, which is incorporated herein by reference.
Some more background of MIP technology are described in, for example, US Pub. 2010/177083 and US Pub. 2010/110067, which are incorporated herein by reference.